One type of prior nonvolatile integrated circuit memory is the erasable programmable read-only memory ("EPROM"). EPROMs frequently use memory cells that have electrically isolated gates (floating gates) such as an enhancement-type n-channel metal-oxide semiconductor field effect transistor (MOSFET) with two gates made of polysilicon material, otherwise known as a FAMOS device. One of the gates in this enhancement-type n-channel MOSFET is not electrically connected to any other part of the circuit (e.g. a floating gate) and the other gate in this enhancement-type n-channel MOSFET functions in the same manner as the gate of a regular enhancement MOSFET (Adel S. Sedra and Kenneth C. Smith, "Microelectronic Circuits", CBS College Publishing, 1982, pp. 776-780.) The EPROM stores information in the memory cells in the form of charge on the floating gates and is programmed by placing a charge on the floating gates. The EPROM can be programmed by a user, and once programmed, the EPROM retains its data until erased. Other memory devices such as a Flash Electrically Erasable Programmable Read Only Memory ("EEPROM") are also user programmable. Flash EEPROMs are also programmed by electrically injecting a charge onto the floating gates.
The EPROM comprises memory cells logically organized by rows and columns which form a memory array. Typically, the rows represent word lines and the columns represent bit lines. By selecting the appropriate word line and bit line, each individual cell may be programmed or read. According to FIG. 1, FAMOS devices 14, 15, 16 and 17 form memory array 11 with FAMOS devices 14 and 15 forming a first row coupled by word line 18a and FAMOS devices 16 and 17 forming a second row coupled by word line 18b and furthermore, FAMOS devices 14 and 16 form a first column coupled by bit line 19a and FAMOS devices 15 and 17 form a second column coupled by bit line 19b.
During a programming operation, once a given memory cell or cells are selected for programming by the Row Decoder and the Column Decoder, a programming voltage, which is channeled through a Load Line Circuit, is applied to the bit line of each selected memory cell. The programming voltage generates a programming current that flows through the selected bit line to increase the drain voltage of the selected memory cell (e.g. FAMOS device), thereby accelerating electrons through the channel of the selected memory cell. Simultaneously, a large positive voltage (greater than the drain voltage) is applied to the control gate of the selected memory cell, thereby establishing an electric field in the insulating oxide of the selected memory cell. This electric field attracts the hot electrons and accelerates them toward the floating gate. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped, thus programming the selected memory cell or cells.
During a reading operation, a voltage is applied to the word line of the selected row. The memory cells that are not programmed will conduct heavily, thus lowering the voltage of its bit line. On the other hand, a programmed cell will not conduct and its bit line remains at a high voltage ( if the bit lines are precharged to high voltages). The column decoder selects one of the bit lines and connects it to the sense amplifier which, in turn, detects the change in voltage of the bit line and thus determines whether the stored bit is a 1 or a 0. Typically, a programmed memory cell stores a "1" and an unprogrammed memory cell stores a "0".
Due to physical and functional limitations of the memory, during programming of the EPROM, the programming current in each bit line must be controlled within certain operating parameters. These physical and functional limitations define a load line "box" within which the current through the memory cell and the voltage across the source/drain current path of the memory cell (current-voltage characteristic curve) must remain in order to ensure the proper programming of the memory cells. In other words, the load line "box" is the voltage/current region where a memory cell can be programmed. The "load line "box" is defined by four points: the minimum source-to-drain voltage/current for fast cells to program, the minimum source-to-drain voltage/current for slow cells to program, the maximum source-to-drain voltage/current to prevent fast cells from snapping back, and the maximum drain-to-source voltage/current that would not cause charge loss. Therefore, in order to ensure proper programming of all the memory cells in the programmable memory array without latchup or charge loss, the Load Line Circuit must provide a load line (or resistance) which operates within the load line "box".
Typical EPROMS have 8 outputs which provide 8 programming paths to allow the user to program 8 bits at a time. Unfortunately, programming only 8 bits at a time takes considerable time to program an entire programmable memory array which typically ranges in size from 16K-1M bits. Furthermore, since the programming of the EPROM device consumes the largest portion of the programmable memory test time during manufacturing, it would be advantageous to program multiple bits on each programming path. Reducing the production test time of these EPROM devices will increase the production through-put thereby reducing the manufacturing costs associated with these EPROM devices.
In an attempt to resolve this issue, the prior art provided a test mode that would allow a tester to program 4 bits per output at a time by selecting four column addresses per output, rather than one. However, by having multiple memory cells share the same load line, the effective load line "box" becomes much smaller and much harder to predict. Unfortunately, when the load line "box" is reduced in size, it becomes difficult to ensure that the fast bits will program, and that substantial substrate current will not cause latchup. Because four times as much current needs to be supplied to the memory array, the resistance of the Load Line Circuit is decreased. The decrease in the resistance of the Load Line Circuit negatively impacts the performance of the programmable memory device by increasing the load seen by the sense amplifier. Furthermore, the sense amplifier requires an extra device to block the high voltage from damaging the sense amplifier. Therefore, it is advantageous to provide an EPROM device that can program multiple bits simultaneously in a reliable manner that enhances the performance of the EPROM device.